1. Field of Invention
The present invention relates to an address transition detection circuit, and in particular, to an address transition detection circuit that generates an address transition detection signal having a prescribed pulse width.
2. Discussion of Related Art
A pulse width of an address transition detection signal maintains a data reading cycle. The address transition detection signal in DRAM is generated from a column address path.
In a static column mode, a data in bitline is outputted in turn according to an input of the column address where a signal synchronized by an address input such as /CAS is required to control a data transmission and an activation of related circuits. In the static mode, the /CAS signal is not inputted again after a second bit but, instead, a variety of controlling signals to access a data are provided by generating an address transition detection signal.
The Address Transition Detection (ATD) circuit into which a column address is inputted generates an ATD signal by detecting the address transition. While the ATD signal is activated, speed of transmitting a data is increased and power consumption is reduced by pre-charging a data bus line up to a fixed level, which is usually VCC/2. FIG. 1 shows a prior art ATD circuit. As shown in FIG. 1, if an address bit AIN inputted into the ATD circuit goes from low to high level, a signal of node N5, which is an output signal of an inverter INV1 indicates low level, and a signal of node N2, which is an output signal of an inverter INV2, indicates high level. The inverters INV1 and INV2 are connected in series. A transmission gate TG1 is turned on and a transmission gate TG2 is turned off by the signals of the node N2 and the node N5. The high level signal of the node N2 is applied to a NAND gate NAND1 through two paths. A first path is a direct path and a second path is a delaying path that consists of inverters INV3 and INV4 and capacitors C1 and C2. Hence, an output signal of the NAND gate NAND 1 becomes a pulse signal having a high level pulse width equal to a time delayed by the delaying path. The pulse signal from the NAND gate NAND1 is outputted as an ATD signal through the turned-on transmission gate TG1.
When an address bit AIN goes from high to low level, a signal of the node N5 becomes high level and the node N2 becomes low level. Hence, the transmission gate TG1 is turned off, while the transmission gate TG2 is turned on. The low level signal of the node N5 is inputted into the NAND gate NAND2 through a direct path and a delaying path consisting of the inverters INV5 and INV6 and the capacitors C3 and C4. An output signal of the NAND gate NAND2 becomes a pulse signal having a high level pulse width equal to a time delayed by the delaying path. Then, the pulse signal from the NAND gate NAND2 is outputted as an ATD signal through the turned on transmission gate TG2.
As described above, the prior art ATD circuit has various problems. If a positive short pulse having a pulse width shorter than a normal address bit is inputted into the related art ATD circuit, the node N5 signal becomes a negative short pulse, which is inputted into the NAND gate NAND2 through the direct path and the delaying path INV5, C3, INV6 and C4. The node N2 signal becomes a positive short pulse, which is inputted into the NAND gate NAND1 through the direct path and the delaying path INV3, C1, INV4 and C2. However, such short pulses are less than a time to respectively turn on or off the transmission gates TG1 and TG2 produce the output signals of the NAND gates NAND1 and NAND2 as ATD signals. Further, the logic values of the NAND gates NAND1 and NAND2 are unreliable when the pulse widths of the short pulses are shorter than the delayed time in the delaying path consisting of the inverters and capacitors in the prior art ATD circuit.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.